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1 ltc3830/ltc3830-1 sn3830 3830fs high power step-down synchronous dc/dc controllers for low voltage operation n high power switching regulator controller for 3.3v-5v to 1.xv-3.xv step-down applications n no current sense resistor required n low input supply voltage range: 3v to 8v n maximum duty cycle > 91% over temperature n all n-channel external mosfets n excellent output regulation: 1% over line, load and temperature variations n high efficiency: over 95% possible n adjustable or fixed 3.3v output (16-pin version) n programmable fixed frequency operation: 100khz to 500khz n external clock synchronization n soft-start (some versions) n low shutdown current: <10 m a n overtemperature protection n available in s8, s16 and ssop-16 packages n cpu power supplies n multiple logic supply generator n distributed power applications n high efficiency power conversion the ltc ? 3830/ltc3830-1 are high power, high effi- ciency switching regulator controllers optimized for 3.3v-5v to 1.xv-3.xv step-down applications. a preci- sion internal reference and feedback system provide 1% output regulation over temperature, load current and line voltage variations. the ltc3830/ltc3830-1 use a synchronous switching architecture with n-channel mosfets. additionally, the chip senses output current through the drain-source resistance of the upper n-channel fet, providing an adjustable current limit without a current sense resistor. the ltc3830/ltc3830-1 operate with an input supply voltage as low as 3v and with a maximum duty cycle of >91% over temperature. they include a fixed frequency pwm oscillator for low output ripple operation. the 200khz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100khz to 500khz. in shutdown mode, the ltc3830 supply current drops to <10 m a. the ltc3830-1 differs from the ltc3830 s8 ver- sion by replacing shutdown with a soft-start function. for a similar, pin compatible dc/dc converter with an output voltage as low as 0.6v, please refer to the ltc3832. , ltc and lt are registered trademarks of linear technology corporation. figure 1. high efficiency 3v-8v to 1.8v power converter + + 0.01 f 15k ss comp gnd fb pv cc2 g1 pv cc1 g2 ltc3830-1 12v 3.3nf 0.1 f 4.7 f m1 si7806dn 4.7 f b320a 220 f 10v 1.8v 9a l 3.2 h m2 si7806dn l: sumida cdep105-3r2mc-88 c out : panasonic eefueod271r c out 270 f 2v 3830 f01 5.1 v in 3v to 8v 12.7k 1% 5.36k 1% load current (a) 40 efficiency (%) 60 80 100 50 70 90 2468 3830 ta02 10 1 03579 v in = 3.3v v out = 1.8v efficiency descriptio u features applicatio s u typical applicatio u
2 ltc3830/ltc3830-1 sn3830 3830fs supply voltage v cc ....................................................................... 9v pv cc1,2 ................................................................ 14v input voltage i fb , i max ............................................... C 0.3v to 14v sense + , sense C , fb, shdn, freqset ....................... C 0.3v to v cc + 0.3v order part number ltc3830es8 t jmax = 125 c, q ja = 130 c/ w absolute axi u rati gs w ww u package/order i for atio uu w s8 part marking 3830 (note 1) junction temperature ........................................... 125 c operating temperature range (note 9) .. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 8 7 6 5 top view g2 v cc /pv cc2 comp shdn g1 pv cc1 gnd fb s8 package 8-lead plastic so order part number LTC3830-1ES8 s8 part marking 38301 1 2 3 4 8 7 6 5 top view g2 v cc /pv cc2 comp ss g1 pv cc1 gnd fb s8 package 8-lead plastic so t jmax = 125 c, q ja = 130 c/ w order part number ltc3830egn ltc3830es t jmax = 125 c, q ja = 130 c/ w (gn) t jmax = 125 c, q ja = 100 c/ w (s) gn package 16-lead plastic ssop s package 16-lead plastic so 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 g1 pv cc1 pgnd gnd sense fb sense + shdn g2 pv cc2 v cc i fb i max freqset comp ss consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units v cc supply voltage l 358 v pv cc pv cc1 , pv cc2 voltage (note 7) l 3 13.2 v v uvlo undervoltage lockout voltage 2.4 2.9 v v fb feedback voltage v comp = 1.25v 1.255 1.265 1.275 v l 1.252 1.265 1.278 v v out output voltage v comp = 1.25v 3.250 3.3 3.350 v l 3.235 3.3 3.365 v d v out output load regulation i out = 0a to 10a (note 6) 2 mv output line regulation v cc = 4.75v to 5.25v 0.1 mv the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc , pv cc1 , pv cc2 = 5v, unless otherwise noted. (note 2) electrical characteristics gn part marking 3830
3 ltc3830/ltc3830-1 sn3830 3830fs symbol parameter conditions min typ max units i vcc supply current figure 2, v shdn = v cc l 0.7 1.6 ma v shdn = 0v l 110 m a i pvcc pv cc supply current figure 2, v shdn = v cc (note 3) l 14 20 ma v shdn = 0v l 0.1 10 m a f osc internal oscillator frequency freqset floating l 160 200 250 khz v sawl v comp at minimum duty cycle 1.2 v v sawh v comp at maximum duty cycle 2.2 v v compmax maximum v comp v fb = 0v, pv cc1 = 8v 2.85 v d f osc / d i freqset frequency adjustment 10 khz/ m a a v error amplifier open-loop dc gain measured from fb to comp, l 46 55 db sense + and sense C floating, (note 4) g m error amplifier transconductance measured from fb to comp, l 520 650 780 m mho sense + and sense C floating, (note 4) i comp error amplifier output sink/source current 100 m a i max i max sink current v imax = v cc 91215 m a (note 10) l 41220 m a i max sink current tempco v imax = v cc (note 6) 3300 ppm/ c v ih shdn input high voltage l 2.4 v v il shdn input low voltage l 0.8 v i in shdn input current v shdn = v cc l 0.1 1 m a i ss soft-start source current v ss = 0v, v imax = 0v, v ifb = v cc l C8 C12 C16 m a i ssil maximum soft-start sink current v imax = v cc , v ifb = 0v, 1.6 ma in current limit v ss = v cc (note 8), pv cc1 = 8v r sense sense input resistance 29.2 k w r sensefb sense to fb resistance 18 k w t r , t f driver rise/fall time figure 2, pv cc1 = pv cc2 = 5v (note 5) l 80 250 ns t nov driver nonoverlap time figure 2, pv cc1 = pv cc2 = 5v (note 5) l 25 120 250 ns dc max maximum g1 duty cycle figure 2, v fb = 0v (note 5), pv cc1 = 8v l 91 95 % the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc , pv cc1 , pv cc2 = 5v, unless otherwise noted. (note 2) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: supply current in normal operation is dominated by the current needed to charge and discharge the external fet gates. this will vary with the ltc3830 operating frequency, operating voltage and the external fets used. note 4: the open-loop dc gain and transconductance from the sense + and sense C pins to comp pin will be (a v )(1.265/3.3) and (g m )(1.265/3.3) respectively. note 5: rise and fall times are measured using 10% and 90% levels. duty cycle and nonoverlap times are measured using 50% levels. note 6: guaranteed by design, not subject to test. note 7: pv cc1 must be higher than v cc by at least 2.5v for the current limit protection circuit to be active. note 8: the current limiting amplifier can sink but cannot source current. under normal (not current limited) operation, the output current will be zero. note 9: the ltc3830e/ltc3830-1e are guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 10: the minimum and maximum limits for i max over temperature includes the intentional temperature coefficient of 3300ppm/ c. this induced temperature coefficient counteracts the typical temperature coefficient of the external power mosfet on-resistance. this results in a relatively flat current limit over temperature for the application.
4 ltc3830/ltc3830-1 sn3830 3830fs typical perfor a ce characteristics uw load regulation output current (a) ?5 v out (v) 3.33 0 3830 g02 3.30 3.28 ?0 ? 5 3.27 3.26 3.34 3.32 3.31 3.29 10 15 t a = 25 c refer to figure 12 line regulation supply voltage (v) 3 v fb (v) ? v fb (mv) 1.267 1.271 1.275 7 3830 g03 1.263 1.259 1.265 1.269 1.273 1.261 1.257 1.255 2 6 10 ? ? 0 4 8 ? ? ?0 4 5 6 8 t a = 25 c output voltage temperature drift temperature ( c) ?0 v out (v) ? v out (mv) 3.33 25 3830 g04 3.30 3.28 ?5 0 50 3.27 3.26 3.34 3.32 3.31 3.29 30 0 ?0 ?0 ?0 40 20 10 ?0 75 100 125 refer to figure 12 output = no load error amplifier transconductance vs temperature temperature (?c) ?0 error amplifier transconductance ( mho) 700 750 800 25 75 3830 g05 650 600 ?5 0 50 100 125 550 500 temperature ( c) ?0 error amplifier sink/source current ( a) 180 25 3830 g06 120 80 ?5 0 50 60 40 200 160 140 100 75 100 125 temperature ( c) ?0 40 error amplifier open-loop gain (db) 45 50 55 60 25 0 25 50 2830 g07 75 100 125 error amplifier sink/source current vs temperature error amplifier open-loop gain vs temperature oscillator frequency vs temperature oscillator frequency vs freqset input current oscillator (v sawh C v sawl ) vs external sync frequency temperature ( c) ?0 160 oscillator frequency (khz) 170 190 200 210 50 250 3831 g08 180 0 ?5 75 100 25 125 220 230 240 freqset floating freqset input current ( a) ?0 0 oscillator frequency (khz) 100 200 300 400 600 ?0 20 ?0 0 3830 g09 10 20 500 t a = 25 c external sync frequency (khz) 100 0.5 v sawh ?v sawl (v) 0.6 0.8 0.9 1.0 1.5 1.2 200 300 3830 g10 0.7 1.3 1.4 1.1 400 500 t a = 25 c
5 ltc3830/ltc3830-1 sn3830 3830fs typical perfor a ce characteristics uw maximum g1 duty cycle vs temperature i max sink current vs temperature output overcurrent protection output current limit threshold vs temperature soft-start source current vs temperature soft-start sink current vs (v ifb C v imax ) temperature ( c) ?0 91 maximum g1 duty cycle (%) 92 94 95 96 50 100 3830 g11 93 0 ?5 75 100 25 125 97 98 99 v fb = 0v refer to figure 3 temperature ( c) ?0 i max sink current ( a) 18 25 3830 g12 12 8 ?5 0 50 6 4 20 16 14 10 75 100 125 output current (a) 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3830 g13 2 4 6 8 10 12 14 output voltage (v) t a = 25 c refer to figure 12 r imax = 20k temperature ( c) ?0 5 output current limit (a) 6 8 9 10 15 12 0 50 75 3830 g14 7 13 14 11 ?5 25 100 125 refer to figure 12 and note 10 of the electrical characteristics r imax = 20k temperature ( c) ?0 soft-start source current ( a) ? 25 3830 g15 ?2 ?4 ?5 0 50 ?5 ?6 ? ?0 ?1 ?3 75 100 125 v ifb ?v imax (mv) ?50 soft-start sink current (ma) 0.75 1.00 1.25 ?5 ?5 3830 g16 0.50 0.25 0 ?25 ?00 50 1.50 1.75 2.00 0 t a = 25 c undervoltage lockout threshold voltage vs temperature v cc operating supply current vs temperature pv cc supply current vs oscillator frequency temperature ( c) ?0 2.0 undervoltage lockout threshold voltage (v) 2.1 2.3 2.4 2.5 3.0 2.7 0 50 75 3830 g17 2.2 2.8 2.9 2.6 ?5 25 100 125 temperature ( c) ?0 v cc operating supply current (ma) 0.8 1.4 1.5 1.6 0 50 75 3830 g18 0.6 1.2 1.0 0.7 1.3 0.5 0.4 1.1 0.9 ?5 25 100 125 freqset floating oscillator frequency (khz) 0 0 pv cc supply current (ma) 10 30 40 50 200 400 500 90 3830 g19 20 100 300 60 70 80 t a = 25 c g1 and g2 loaded with 6800pf, pv cc1,2 = 12v g1 and g2 loaded with 1000pf, pv cc1,2 = 5v g1 and g2 loaded with 6800pf, pv cc1,2 = 5v
6 ltc3830/ltc3830-1 sn3830 3830fs typical perfor a ce characteristics uw pv cc supply current vs gate capacitance g1 rise/fall time vs gate capacitance transient response gate capacitance at g1 and g2 (nf) 0 pv cc supply current (ma) 30 40 50 8 3830 g20 20 10 0 123 45 67 9 10 t a = 25 c pv cc1,2 = 12v pv cc1,2 = 5v gate capacitance at g1 and g2 (nf) 0 g1 rise/fall time (ns) 120 160 200 8 3830 g21 80 40 100 140 180 60 20 0 2 1 4 3 67 9 5 10 t a = 25 c t f at pv cc1,2 = 12v t r at pv cc1,2 = 12v t r at pv cc1,2 = 5v t f at pv cc1,2 = 5v uu u pi fu ctio s g1 (pin 1/pin 1/pin 1): top gate driver output. connect this pin to the gate of the upper n-channel mosfet, q1. this output swings from pgnd to pv cc1 . it remains low if g2 is high or during shutdown mode. pv cc1 (pin 2/pin 2/pin 2): power supply input for g1. connect this pin to a potential of at least v in + v gs(on)(q1) . this potential can be generated using an external supply or charge pump. pgnd (pin 3/pin 3/pin 3): power ground. both drivers return to this pin. connect this pin to a low impedance ground in close proximity to the source of q2. refer to the layout consideration section for more details on pcb layout techniques. the ltc3830-1 and the 8-lead ltc3830 have pgnd and gnd tied together internally at pin 3. gnd (pin 4/pin 3/pin 3): signal ground. all low power internal circuitry returns to this pin. to minimize regula- tion errors due to ground currents, connect gnd to pgnd right at the ltc3830. sense C , fb, sense + (pins 5, 6, 7/pin 4/pin 4): these three pins connect to the internal resistor divider and input of the error amplifier. to use the internal divider to set the output voltage to 3.3v, connect sense + to the positive terminal of the output capacitor and sense C to the nega- tive terminal. fb should be left floating. to use an external resistor divider to set the output voltage, float sense + and sense C and connect the external resistor divider to fb. the internal resistor divider is not included in the ltc3830-1 and the 8-lead ltc3830. shdn (pin 8/pin 5/na): shutdown. a ttl compatible low level at shdn for longer than 100 m s puts the ltc3830 into shutdown mode. in shutdown, g1 and g2 go low, all internal circuits are disabled and the quiescent current drops to 10 m a max. a ttl compatible high level at shdn allows the part to operate normally. this pin also doubles as an external clock input to synchronize the internal oscillator with an external clock. the shutdown function is disabled in the ltc3830-1. ss (pin 9/na/pin 5): soft-start. connect this pin to an external capacitor, c ss , to implement a soft-start function. if the ltc3830 goes into current limit, c ss is discharged to reduce the duty cycle. c ss must be selected such that during power-up, the current through q1 will not exceed the current limit level. the soft-start function is disabled in the 8-lead ltc3830. comp (pin 10/pin 6/pin 6): external compensation. this pin internally connects to the output of the error amplifier and input of the pwm comparator. use a rc + c network at this pin to compensate the feedback loop to provide optimum transient response. (16-lead ltc3830/8-lead ltc3830/ltc3830-1) v out 50mv/div i load 2av/div 50 m s/div 3830 g22.tif
7 ltc3830/ltc3830-1 sn3830 3830fs uu u pi fu ctio s freqset (pin 11/na/na): frequency set. use this pin to adjust the free-running frequency of the internal oscillator. with the pin floating, the oscillator runs at about 200khz. a resistor from freqset to ground speeds up the oscil- lator; a resistor to v cc slows it down. i max (pin 12/na/na): current limit threshold set. i max sets the threshold for the internal current limit compara- tor. if i fb drops below i max with g1 on, the ltc3830 goes into current limit. i max has an internal 12 m a pull-down to gnd. connect this pin to the main v in supply at the drain of q1, through an external resistor to set the current limit threshold. connect a 0.1 m f decoupling capacitor across this resistor to filter switching noise. i fb (pin 13/na/na): current limit sense. connect this pin to the switching node at the source of q1 and the drain of q2 through a 1k resistor. the 1k resistor is required to prevent voltage transients from damaging i fb .this pin is used for sensing the voltage drop across the upper n-channel mosfet, q1. v cc (pin 14/pin 7/pin 7): power supply input. all low power internal circuits draw their supply from this pin. connect this pin to a clean power supply, separate from the main v in supply at the drain of q1. this pin requires a 4.7 m f bypass capacitor. the ltc3830-1 and the 8-lead ltc3830 have v cc and pv cc2 tied together at pin 7 and require a 10 m f bypass capacitor to gnd. pv cc2 (pin 15/pin 7/pin 7): power supply input for g2. connect this pin to the main high power supply. g2 (pin 16/pin 8/pin 8): bottom gate driver output. connect this pin to the gate of the lower n-channel mosfet, q2. this output swings from pgnd to pv cc2 . it remains low when g1 is high or during shutdown mode. to prevent output undershoot during a soft-start cycle, g2 is held low until g1 first goes high. (ffbg in block diagram.) block diagra w + + + r s pv cc1 g1 pv cc2 g2 pgnd fb sense + v ref v ref ?3% v ref + 3% 18k 11.2k sense 3830 bd bg q q r por ffbg enable g2 sq + pwm qss v ref v ref ?3% v ref + 3% max min err 12 a internal oscillator 100 s delay shdn freqset comp ss power down disable gate drive logic and thermal shutdown + cc 12 a i max i fb v cc gnd
8 ltc3830/ltc3830-1 sn3830 3830fs test circuits fb ss freqset comp i max nc nc nc nc g1 g2 shdn v cc v shdn v cc pv cc2 pv cc1 pv cc i fb 6800pf 6800pf 3830 f02 gnd pgnd sense ltc3830 sense + comp fb v comp v fb g1 g2 i fb v cc pv cc1 5v pv cc2 6800pf 0.1 f 10 f 6800pf g1 rise/fall g2 rise/fall 3830 f03 i max gnd pgnd ltc3830 + figure 2 figure 3 applicatio s i for atio wu uu overview the ltc3830 is a voltage mode feedback, synchronous switching regulator controller (see block diagram) de- signed for use in high power, low voltage step-down (buck) converters. it includes an onboard pwm generator, a precision reference trimmed to 0.8%, two high power mosfet gate drivers and all necessary feedback and control circuitry to form a complete switching regulator circuit. the pwm loop nominally runs at 200khz. the 16-lead versions of the ltc3830 include a current limit sensing circuit that uses the topside external n-channel power mosfet as a current sensing element, eliminating the need for an external sense resistor. also included in the 16-lead version and the ltc3830-1 is an internal soft-start feature that requires only a single external capacitor to operate. in addition, 16-lead parts feature an adjustable oscillator that can free run or synchronize to external signal with frequencies from 100khz to 500khz, allowing added flexibility in external component selection. the 8-lead version does not in- clude current limit, internal soft-start and frequency adjustability. the ltc3830-1 does not include current limit, frequency adjustability, external synchronization and the shutdown function. theory of operation primary feedback loop the ltc3830/ltc3830-1 sense the output voltage of the circuit at the output capacitor and feeds this voltage back to the internal transconductance error amplifier, err, through a resistor divider network. the error amplifier compares the resistor-divided output voltage to the inter- nal 1.265v reference and outputs an error signal to the pwm comparator. this error signal is compared with a fixed frequency ramp waveform, from the internal oscil- lator, to generate a pulse width modulated signal. this pwm signal drives the external mosfets through the g1 and g2 pins. the resulting chopped waveform is filtered by l o and c out which closes the loop. loop compensation is achieved with an external compensation network at the comp pin, the output node of the error amplifier. min, max feedback loops two additional comparators in the feedback loop provide high speed output voltage correction in situations where the error amplifier may not respond quickly enough. min compares the feedback signal to a voltage 40mv below the internal reference. if the signal is below the comparator threshold, the min comparator overrides the error ampli- fier and forces the loop to maximum duty cycle, >91%.
9 ltc3830/ltc3830-1 sn3830 3830fs applicatio s i for atio wu uu similarly, the max comparator forces the output to 0% duty cycle if the feedback signal is greater than 40mv above the internal reference. to prevent these two com- parators from triggering due to noise, the min and max comparators response times are deliberately delayed by two to three microseconds. these two comparators help prevent extreme output perturbations with fast output load current transients, while allowing the main feedback loop to be optimally compensated for stability. thermal shutdown the ltc3830/ltc3830-1 have a thermal protection cir- cuit that disables both gate drivers if activated. if the chip junction temperature reaches 150 c, both g1 and g2 are pulled low. g1 and g2 remain low until the junction temperature drops below 125 c, after which, the chip resumes normal operation. soft-start and current limit the 16-lead ltc3830 devices include a soft-start circuit that is used for start-up and current limit operation. the ltc3830-1 only has the soft-start function; the current limit function is disabled. the 8-lead ltc3830 has both the soft-start and current limit function disabled. the ss pin requires an external capacitor, c ss , to gnd with the value determined by the required soft-start time. an internal 12 m a current source is included to charge c ss . during power-up, the comp pin is clamped to a diode drop (b-e junction of qss in the block diagram) above the voltage at the ss pin. this prevents the error amplifier from forcing the loop to maximum duty cycle. the ltc3830/ltc3830-1 operate at low duty cycle as the ss pin rises above 0.6v (v comp ? 1.2v). as ss continues to rise, qss turns off and the error amplifier takes over to regulate the output. the min comparator is disabled during soft-start to prevent it from overriding the soft-start function. the 16-lead ltc3830 devices include yet another feed- back loop to control operation in current limit. just before every falling edge of g1, the current comparator, cc, samples and holds the voltage drop measured across the external upper mosfet, q1, at the i fb pin. cc compares the voltage at i fb to the voltage at the i max pin. as the peak current rises, the measured voltage across q1 increases due to the drop across the r ds(on) of q1. when the voltage at i fb drops below i max , indicating that q1s drain current has exceeded the maximum level, cc starts to pull current out of c ss , cutting the duty cycle and controlling the output current level. the cc comparator pulls current out of the ss pin in proportion to the voltage difference between i fb and i max . under minor overload conditions, the ss pin falls gradually, creating a time delay before current limit takes effect. very short, mild overloads may not affect the output voltage at all. more significant overload conditions allow the ss pin to reach a steady state, and the output remains at a reduced voltage until the overload is re- moved. serious overloads generate a large overdrive at cc, allowing it to pull ss down quickly and preventing damage to the output components. by using the r ds(on) of q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. this helps minimize the number of components in the high current path. the current limit threshold can be set by connecting an external resistor r imax from the i max pin to the main v in supply at the drain of q1. the value of r imax is determined by: r imax = (i lmax )(r ds(on)q1 )/i imax where: i lmax = i load + (i ripple /2) i load = maximum load current i ripple = inductor ripple current = ()() () ()( ) vv v flv in out out osc o in f osc = ltc3830 oscillator frequency = 200khz l o = inductor value r ds(on)q1 = on-resistance of q1 at i lmax i imax = internal 12 m a sink current at i max
10 ltc3830/ltc3830-1 sn3830 3830fs the r ds(on) of q1 usually increases with temperature. to keep the current limit threshold constant, the internal 12 m a sink current at i max is designed with a positive temperature coefficient to provide first order correction for the temperature coefficient of r ds(on)q1 . in order for the current limit circuit to operate properly and to obtain a reasonably accurate current limit threshold, the i imax and i fb pins must be kelvin sensed at q1s drain and source pins. in addition, connect a 0.1 m f decoupling capacitor across r imax to filter switching noise. other- wise, noise spikes or ringing at q1s source can cause the actual current limit to be greater than the desired current limit set point. due to switching noise and variation of r ds(on) , the actual current limit trip point is not highly accurate. the current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. the exact current level where the limiting circuit begins to take effect will vary from unit to unit as the r ds(on) of q1 varies. typically, r ds(on) varies as much as 40% and with 25% variation on the ltc3830s i max current, this can give a 65% variation on the current limit threshold. the r ds(on) is high if the v gs applied to the mosfet is low. this occurs during power up, when pv cc1 is ramping up. to prevent the high r ds(on) from activating the current limit, the ltc3830 disables the current limit circuit if pv cc1 is less than 2.5v above v cc . to ensure proper operation of the current limit circuit, pv cc1 must be at least 2.5v above v cc when g1 is high. pv cc1 can go low when g1 is low, allowing the use of an external charge pump to power pv cc1 . oscillator frequency the ltc3830 includes an onboard current controlled oscillator that typically free-runs at 200khz. the oscillator frequency can be adjusted by forcing current into or out of the freqset pin. with the pin floating, the oscillator runs at about 200khz. every additional 1 m a of current into/out of the freqset pin decreases/increases the frequency by 10khz. the pin is internally servoed to 1.265v, connecting a 50k resistor from freqset to ground forces 25 m a out of the pin, causing the internal oscillator to run at approxi- mately 450khz. forcing an external 10 m a current into freqset cuts the internal frequency to 100khz. an inter- nal clamp prevents the oscillator from running slower than about 50khz. tying freqset to v cc forces the chip to run at this minimum speed. the ltc3830-1 and the 8-lead ltc3830 do not have this frequency adjustment function. shutdown the ltc3830 includes a low power shutdown mode, controlled by the logic at the shdn pin. a high at shdn allows the part to operate normally. a low level at shdn for more than 100 m s forces the ltc3830 into shutdown mode. in this mode, all internal switching stops, the comp and ss pins pull to ground and q1 and q2 turn off. the ltc3830 supply current drops to <10 m a, although off- state leakage in the external mosfets may cause the total v in current to be some what higher, especially at elevated temperatures. if shdn returns high, the ltc3830 reruns a soft-start cycle and resumes normal operation. the ltc3830-1 does not have this shutdown function. external clock synchronization the ltc3830 shdn pin doubles as an external clock input for applications that require a synchronized clock. an internal circuit forces the ltc3830 into external synchro- nization mode if a negative transition at the shdn pin is detected. in this mode, every negative transition on the shdn pin resets the internal oscillator and pulls the ramp signal low, this forces the ltc3830 internal oscillator to lock to the external clock frequency. the ltc3830-1 does not have this external synchronization function. applicatio s i for atio wu uu + + 12 13 ltc3830 cc 12 a 0.1 f q2 c out 3830 f04 c in v in v out g2 i max r imax i fb 1k + q1 l o g1 figure 4. current limit setting
11 ltc3830/ltc3830-1 sn3830 3830fs the ltc3830 internal oscillator can be externally synchro- nized from 100khz to 500khz. frequencies above 300khz can cause a decrease in the maximum obtainable duty cycle as rise/fall time and propagation delay take up a larger percentage of the switch cycle. circuits using these frequencies should be checked carefully in applications where operation near dropout is importantlike 3.3v to 2.5v converters. the low period of this clock signal must not be >100 m s, or else the ltc3830 enters shutdown mode. figure 5 describes the operation of the external synchro- nization function. a negative transition at the shdn pin forces the internal ramp signal low to restart a new pwm cycle. notice that with the traditional sync method, the ramp amplitude is lowered as the external clock frequency goes higher. the effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. as a result, the loop crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient. to overcome this problem, the ltc3830 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. input supply considerations/charge pump the 16-lead ltc3830 requires four supply voltages to operate: v in for the main power input, pv cc1 and pv cc2 for mosfet gate drive and a clean, low ripple v cc for the ltc3830 internal circuitry (figure 6). the ltc3830-1 and the 8-lead ltc3830 have the pv cc2 and v cc pins tied together inside the package (figure 7). this pin, brought out as v cc /pv cc2 , has the same low ripple requirements as the 16-lead part, but must also be able to supply the gate drive current to q2. in many applications, v cc can be powered from v in through an rc filter. this supply can be as low as 3v. the low quiescent current (typically 800 m a) allows the use of relatively large filter resistors and correspondingly small applicatio s i for atio wu uu shdn 200khz free running ramp signal traditional sync method with early ramp termination ltc3830 keeps ramp amplitude constant under sync ramp signal with ext sync ramp amplitude adjusted 3830 f05 figure 5. external synchronization operation 3830 f6 + v cc pv cc2 pv cc1 v in g1 q1 c out v out q2 l o g2 internal circuitry ltc3830 (16-lead) 3830 f7 + v cc /pv cc2 pv cc1 v in g1 q1 c out v out q2 l o g2 internal circuitry ltc3830 (8-lead) figure 6. 16-lead power supplies figure 7. 8-lead power supplies
12 ltc3830/ltc3830-1 sn3830 3830fs filter capacitors. 100 w and 4.7 m f usually provide ad- equate filtering for v cc . for best performance, connect the 4.7 m f bypass capacitor as close to the ltc3830 v cc pin as possible. gate drive for the top n-channel mosfet q1 is supplied from pv cc1 . this supply must be above v in (the main power supply input) by at least one power mosfet v gs(on) for efficient operation. an internal level shifter allows pv cc1 to operate at voltages above v cc and v in , up to 14v maxi- mum. this higher voltage can be supplied with a separate supply, or it can be generated using a charge pump. gate drive for the bottom mosfet q2 is provided through pv cc2 for the 16-lead ltc3830 or v cc /pv cc2 for the ltc3830-1 and the 8-lead ltc3830. this supply only needs to be above the power mosfet v gs(on) for efficient operation. pv cc2 can also be driven from the same supply/ charge pump for the pv cc1 , or it can be connected to a lower supply to improve efficiency. figure 8 shows a tripling charge pump circuit that can be used to provide 2v in and 3v in gate drive for the external top and bottom mosfets respectively. these should fully enhance mosfets with 5v logic level thresholds. this circuit provides 3v in C 3v f to pv cc1 while q1 is on and 2v in C 2v f to pv cc2 where v f is the forward voltage of the schottky diodes. the circuit requires the use of schottky diodes to minimize forward drop across the diodes at start-up. the tripling charge pump circuit can rectify any ringing at the drain of q2 and provide more than 3v in at pv cc1 ; a 12v zener diode should be included from pv cc1 to pgnd to prevent transients from damaging the circuitry at pv cc1 or the gate of q1. care should be taken when using a charge pump to power pv cc1 in applications with low v cc supply voltages (less than 4v) or high switching frequencies. the charge pump capacitors refresh when the g2 pin goes high and the switch node is pulled low by q2. the g2 on-time becomes narrow when ltc3830 operates at maximum duty cycle (95% typical), which can occur if the input supply rises more slowly than the soft-start capacitor or the input voltage droops during load transients. if the g2 on-time gets so narrow that the switch node fails to pull completely to ground, the charge pump voltage may collapse or fail to start, causing excessive dissipation in external mosfet q1. this is most likely with low v cc voltages and high switching frequencies, coupled with large external mosfets which slow the g2 and switch node slew rates. workarounds include: ? increasing the soft-start capacitor to limit the duty cycle at start up ? using smaller mosfets with lower gate capacitance (where possible) to reduce the g2 rise/fall time and switch node slew rates ? using an external higher voltage supply to power pv cc1 if available another alternative is to add an external circuit to limit the duty cycle when pv cc1 is low, as shown in figure 9b. if the charge pump is not running, pv cc1 will be less than or equal to v cc and the voltage at the soft-start pin will be about (v cc /6 + v be ). this is about 1.2v with a v cc of 3.3v, which limits the duty cycle to about 50% and allows the charge pump to start up. once pv cc1 rises higher than (v cc + v tq3 ), the voltage at the soft-start pin goes high and the limit on duty cycle is removed. for applications with a 5v or higher v in supply, pv cc2 can be tied to v in if a logic level mosfet is used. pv cc1 can be supplied using a doubling charge pump as shown in figure 9a. this circuit provides 2v in C v f to pv cc1 while q1 is on. applicatio s i for atio wu uu figure 8. tripling charge pump ltc3830 3830 f08 + d z 12v 1n5242 10 f g1 g2 0.1 f q1 l o q2 c out v out 0.1 f pv cc2 1n5817 1n5817 1n5817 pv cc1 v in
13 ltc3830/ltc3830-1 sn3830 3830fs figure 12 shows a typical 5v to 3.3v application using a doubling charge pump to generate pv cc1 . power mosfets two n-channel power mosfets are required for most ltc3830 circuits. these should be selected based primarily on threshold voltage and on-resistance consid- erations. thermal dissipation is often a secondary con- cern in high efficiency designs. the required mosfet threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. in 3.3v input designs where an auxiliary 12v supply is available to power pv cc1 and pv cc2 , standard mosfets with r ds(on) specified at v gs = 5v or 6v can be used with good results. the current drawn from this supply varies with the mosfets used and the ltc3830s operating frequency, but is generally less than 50ma. ltc3830 applications that use 5v or lower v in voltage and a doubling/tripling charge pump to generate pv cc1 and pv cc2 , do not provide enough gate drive voltage to fully enhance standard power mosfets. under this condition, the effective mosfet r ds(on) may be quite high, raising the dissipation in the fets and reducing efficiency. logic level fets are the recommended choice for 5v or lower voltage systems. logic level fets can be fully enhanced with a doubler/tripling charge pump and will operate at maximum efficiency. after the mosfet threshold voltage is selected, choose the r ds(on) based on the input voltage, the output voltage, allowable power dissipation and maximum output current. in a typical ltc3830 circuit, operating in continuous mode, the average inductor current is equal to the output load current. this current flows through either q1 or q2 with the power dissipation split up according to the duty cycle: dc q v v dc q v v vv v out in out in in out in () () 1 21 = == the r ds(on) required for a given conduction loss can now be calculated by rearranging the relation p = i 2 r. r p dc q i vp vi r p dc q i vp vv i ds on q max q load in max q out load ds on q max q load in max q in out load () () () () () () ()( ) ( ) ()( ) ( )( ) 1 1 2 1 2 2 2 2 2 2 1 2 == == applicatio s i for atio wu uu ltc3830 3830 f09a + d z 12v 1n5242 q1 l o q2 c out v out 0.1 f pv cc2 optional use for v in 3 7v mbr0530t1 pv cc1 g1 g2 v in figure 9a. doubling charge pump ltc3830 ss 3830 f09b + q1 q3 bss284 r1 1m l o q2 c out v out 0.1 f pv cc2 10 f d1 d2 pv cc1 g1 g2 v in r2 200k q4 3906 figure 9b. duty cycle clamp circuit
14 ltc3830/ltc3830-1 sn3830 3830fs p max should be calculated based primarily on required efficiency or allowable thermal dissipation. a typical high efficiency circuit designed for 5v input and 3.3v at 10a output might allow no more than 3% efficiency loss at full load for each mosfet. assuming roughly 90% efficiency at this current level, this gives a p max value of: (3.3v)(10a/0.9)(0.03) = 1.1w per fet and a required r ds(on) of: r vw va r vw vva ds on q ds on q () () ()(. ) ( . )( ) . ()(. ) (.)( ) . 1 2 2 2 511 33 10 0 017 511 53310 0 032 ==w ==w note that the required r ds(on) for q2 is roughly twice that of q1 in this example. this application might specify a single 0.03 w device for q2 and parallel two more of the same devices to form q1. note also that while the required r ds(on) values suggest large mosfets, the power dissi- pation numbers are only 1.1w per device or less; large to-220 packages and heat sinks are not necessarily required in high efficiency applications. siliconix si4410dy or international rectifier irf7413 (both in so-8) or siliconix sud50n03-10 (to-252) or on semiconductor mtd20n03hdl (dpak) are small footprint surface mount devices with r ds(on) values below 0.03 w at 5v of v gs that work well in ltc3830 circuits. using a higher p max value in the r ds(on) calculations generally decreases the mosfet cost and the circuit efficiency and increases the mosfet heat sink requirements. table 1 highlights a variety of power mosfets for use in ltc3830 applications. inductor selection the inductor is often the largest component in an ltc3830 design and must be chosen carefully. choose the inductor value and type based on output slew rate requirements. the maximum rate of rise of inductor current is set by the inductors value, the input-to-output voltage differential and the ltc3830s maximum duty cycle. in a typical 5v input, 3.3v output application, the maximum rise time will be: dc v v ll a s max in out oo ( ) . = m 1 615 applicatio s i for atio wu uu table 1. recommended mosfets for ltc3830 applications typical input r ds(on) capacitance parts at 25 c (m w ) rated current (a) c iss (pf) q jc ( c/w) t jmax ( c) siliconix sud50n03-10 19 15 at 25 c 3200 1.8 175 to-252 10 at 100 c siliconix si4410dy 20 10 at 25 c 2700 150 so-8 8 at 70 c on semiconductor mtd20n03hdl 35 20 at 25 c 880 1.67 150 dpak 16 at 100 c fairchild fds6670a 8 13 at 25 c 3200 25 150 s0-8 fairchild fds6680 10 11.5 at 25 c 2070 25 150 so-8 on semiconductor mtb75n03hdl 9 75 at 25 c 4025 1 150 dd pak 59 at 100 c ir irl3103s 19 64 at 25 c 1600 1.4 175 dd pak 45 at 100 c ir irlz44 28 50 at 25 c 3300 1 175 to-220 36 at 100 c fuji 2sk1388 37 35 at 25 c 1750 2.08 150 to-220 note: please refer to the manufacturers data sheet for testing conditions and detailed information.
15 ltc3830/ltc3830-1 sn3830 3830fs where l o is the inductor value in m h. with proper fre- quency compensation, the combination of the inductor and output capacitor values determine the transient recov- ery time. in general, a smaller value inductor improves transient response at the expense of ripple and inductor core saturation rating. a 2 m h inductor has a 0.81a/ m s rise time in this application, resulting in a 6.2 m s delay in responding to a 5a load current step. during this 6.2 m s, the difference between the inductor current and the output current is made up by the output capacitor. this action causes a temporary voltage droop at the output. to minimize this effect, the inductor value should usually be in the 1 m h to 5 m h range for most 5v input ltc3830 circuits. to optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. peak current in the inductor will be equal to the maximum output load current plus half of the peak-to- peak inductor ripple current. ripple current is set by the inductor value, the input and output voltage and the operating frequency. the ripple current is approximately equal to: i vv v flv ripple in out out osc o in = - ()() f osc = ltc3830 oscillator frequency = 200khz l o = inductor value solving this equation with our typical 5v to 3.3v applica- tion with a 2 m h inductor, we get: (.). . 53333 200 2 5 28 vvv khz h v a p m = -p peak inductor current at 10a load: 10a + (2.8a/2) = 11.4a the ripple current should generally be between 10% and 40% of the output current. the inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short-circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. inductors with gradual saturation characteristics are often the best choice. input and output capacitors a typical ltc3830 design places significant demands on both the input and the output capacitors. during normal steady load operation, a buck converter like the ltc3830 draws square waves of current from the input supply at the switching frequency. the peak current value is equal to the output load current plus 1/2 the peak-to-peak ripple cur- rent. most of this current is supplied by the input bypass capacitor. the resulting rms current flow in the input capacitor heats it and causes premature capacitor failure in extreme cases. maximum rms current occurs with 50% pwm duty cycle, giving an rms current value equal to i out /2. a low esr input capacitor with an adequate ripple current rating must be used to ensure reliable operation. note that capacitor manufacturers ripple cur- rent ratings are often based on only 2000 hours (3 months) lifetime at rated temperature. further derating of the input capacitor ripple current beyond the manufacturers speci- fication is recommended to extend the useful life of the circuit. lower operating temperature has the largest effect on capacitor longevity. applicatio s i for atio wu uu
16 ltc3830/ltc3830-1 sn3830 3830fs the output capacitor in a buck converter under steady- state conditions sees much less ripple current than the input capacitor. peak-to-peak current is equal to inductor ripple current, usually 10% to 40% of the total load current. output capacitor duty places a premium not on power dissipation but on esr. during an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the ltc3830 adjusts the inductor current to the new value. esr in the output capacitor results in a step in the output voltage equal to the esr value multiplied by the change in load current. an 5a load step with a 0.05 w esr output capacitor results in a 250mv output voltage shift; this is 7.6% of the output voltage for a 3.3v supply! because of the strong relationship between output capacitor esr and output load transient response, choose the output capaci- tor for esr, not for capacitance value. a capacitor with suitable esr will usually have a larger capacitance value than is needed to control steady-state output ripple. electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and esr can be used effectively in ltc3830 applications. os-con electrolytic capacitors from sanyo and other manufactur- ers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. surface mount applications can use either electrolytic or dry tantalum capacitors. tantalum capacitors must be surge tested and specified for use in switching power supplies. low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. other capacitors that can be used include the sanyo poscap and mv-wx series. a common way to lower esr and raise ripple current capability is to parallel several capacitors. a typical ltc3830 application might exhibit 5a input ripple cur- rent. sanyo os-con capacitors, part number 10sa220m (220 m f/10v), feature 2.3a allowable ripple current at 85 c; three in parallel at the input (to withstand the input ripple current) meet the above requirements. similarly, sanyo poscap 4tpb470m (470 m f/4v) capacitors have a maximum rated esr of 0.04 w ; three in parallel lower the net output capacitor esr to 0.013 w . feedback loop compensation the ltc3830 voltage feedback loop is compensated at the comp pin, which is the output node of the error amplifier. the feedback loop is generally compensated with an rc + c network from comp to gnd as shown in figure 10a. loop stability is affected by the values of the inductor, the output capacitor, the output capacitor esr, the error amplifier transconductance and the error amplifier com- pensation network. the inductor and the output capacitor create a double pole at the frequency: flc lc o out =p [] 12 / ( )( ) the esr of the output capacitor and the output capacitor value form a zero at the frequency: f esr c esr out =p [] 12 / ( )( ) the compensation network used with the error amplifier must provide enough phase margin at the 0db crossover frequency for the overall open-loop transfer function. the zero and pole from the compensation network are: f z = 1/[2 p (r c )(c c )] and f p = 1/[2 p (r c )(c1)] respectively applicatio s i for atio wu uu 3830 f10a ltc3830 v ref r1 sense r2 c2 sense + + 5 v fb 6 comp 10 7 c1 c c r c err figure 10a. compensation pin hook-up
17 ltc3830/ltc3830-1 sn3830 3830fs applicatio s i for atio wu uu figure 10b shows the bode plot of the overall transfer function. when low esr output capacitors (sanyo os-con) are used, the esr zero can be high enough in frequency that it provides little phase boost at the loop crossover fre- quency. as a result, the phase margin becomes inad- equate and the load transient is not optimized. to resolve this problem, a small capacitor can be connected between the top of the resistor divider network and the v fb pin to create a pole-zero pair in the loop compensation. the zero location is prior to the pole location and thus, phase lead can be added to boost the phase margin at the loop crossover frequency. the pole and zero locations are located at: f zc2 = 1/[2 p (r2)(c2)] and f pc2 = 1/[2 p (r1||r2)(c2)] where r1||r2 is the parallel combination resistance of r1 and r2. choose c2 so that the zero is located at a lower frequency compared to f co and the pole location is high enough that the closed loop has enough phase margin for stability. figure 10c shows the bode plot using phase lead compensation around the ltc3830 resistor divider network. note: this technique is effective only when r1 >> r2 i.e., at high output voltages only so that the pole and zero are sufficiently separated. although a mathematical approach to frequency compen- sation can be used, the added complication of input and/or output filters, unknown capacitor esr, and gross operat- ing point changes with input voltage, load current varia- tions, all suggest a more practical empirical method. this can be done by injecting a transient current at the load and using an rc network box to iterate toward the final values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. table 2 shows the suggested compensation component value for 5v to 3.3v applications based on sanyo os-con 4sp820m low esr output capacitors. table 2. recommended compensation network for 5v to 3.3v applications using multiple paralleled 820 m f sanyo os-con 4sp820m output capacitors l1 ( m h) c out ( m f) r c (k w )c c (nf) c1 (pf) c2 (pf) 1.2 1640 6.2 3.3 470 1000 1.2 2460 12 3.3 470 1000 1.2 4100 12 1.8 220 1000 2.4 1640 15 2.7 330 1000 2.4 2460 20 1.0 220 1000 2.4 4100 36 1.0 220 1000 4.7 1640 30 1.8 330 1000 4.7 2460 36 1.0 180 1000 4.7 4100 82 1.0 180 1000 loop gain loop gain 3830 f10b 3830 f10c f z f z f lc f lc f zc2 f co f p f pc2 f esr f esr f co f p frequency frequency 20db/decade 20db/decade f sw = ltc3830 switching frequency f co = closed-loop crossover frequency f sw = ltc3830 switching frequency f co = closed-loop crossover frequency figure 10b. bode plot of the ltc3830 overall transfer function figure 10c. bode plot of the ltc3830 overall transfer function using a low esr output capacitor
18 ltc3830/ltc3830-1 sn3830 3830fs table 3 shows the suggested compensation component values for 5v to 3.3v applications based on 470 m f sanyo poscap 4tpb470m output capacitors. table 3. recommended compensation network for 5v to 3.3v applications using multiple paralleled 470 m f sanyo poscap 4tpb470m output capacitors l1 ( m h) c out ( m f) r c (k w )c c (nf) c1 (pf) 1.2 1410 6.8 4.7 33 1.2 2820 15 2.2 33 1.2 4700 22 2.2 33 2.4 1410 18 10 33 2.4 2820 43 2.2 33 2.4 4700 62 2.2 10 4.7 1410 43 10 10 4.7 2820 91 33 10 4.7 4700 150 10 10 table 4 shows the suggested compensation component values for 5v to 3.3v applications based on 1500 m f sanyo mv-wx output capacitors. table 4. recommended compensation network for 5v to 3.3v applications using multiple paralleled 1500 m f sanyo mv-wx output capacitors l1 ( m h) c out ( m f) r c (k w )c c (nf) c1 (pf) 1.2 4500 22 1.5 120 1.2 6000 30 1 82 1.2 9000 39 0.47 56 2.4 4500 51 1 56 2.4 6000 62 1 33 2.4 9000 82 0.47 27 4.7 4500 100 3.3 15 4.7 6000 150 0.47 15 4.7 9000 200 0.47 15 layout considerations when laying out the printed circuit board, use the follow- ing checklist to ensure proper operation of the ltc3830. these items are also illustrated graphically in the layout diagram of figure 11. the thicker lines show the high current paths. note that at 10a current levels or above, current density in the pc board itself is a serious concern. traces carrying high current should be as wide as pos- sible. for example, a pcb fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10a. 1. in general, layout should begin with the location of the power devices. be sure to orient the power circuitry so that a clean power flow path is achieved. conductor widths should be maximized and lengths minimized. after you are satisfied with the power path, the control circuitry should be laid out. it is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. the gnd and pgnd pins should be shorted directly at the ltc3830. this helps to minimize internal ground dis- turbances in the ltc3830 and prevent differences in ground potential from disrupting internal circuit operation. this connection should then tie into the ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. this is not always practical, however, due to physical constraints. another reasonably good point to make this connection is between the output capacitors and the source connection of the bottom mosfet q2. do not tie this single point ground in the trace run between the q2 source and the input capacitor ground, as this area of the ground plane will be very noisy. applicatio s i for atio wu uu
19 ltc3830/ltc3830-1 sn3830 3830fs 3. the small-signal resistors and capacitors for frequency compensation and soft-start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. do not connect these parts to the ground plane! 4. the v cc , pv cc1 and pv cc2 decoupling capacitors should be as close to the ltc3830 as possible. the 4.7 m f and 1 m f bypass capacitors shown at v cc , pv cc1 and pv cc2 will help provide optimum regulation performance. 5. the (+) plate of c in should be connected as close as possible to the drain of the upper mosfet, q1. an addi- tional 1 m f ceramic capacitor between v in and power ground is recommended. 6. the sense and v fb pins are very sensitive to pickup from the switching node. care should be taken to isolate sense and v fb from possible capacitive coupling to the inductor switching signal. connecting the sense + and sense C close to the load can significantly improve load regulation. 7. kelvin sense i max and i fb at q1s drain and source pins. pv cc1 g1 i max i fb sense + g2 fb sense freqset shdn comp ss v cc ltc3830 pv cc2 gnd pgnd + + 1 f gnd gnd nc 100 1k v in q1a q2 pgnd q1b c in + c out 3830 f11 v out l o c ss c1 c c 4.7 f nc r c 1 f 0.1 f pgnd pv cc figure 11. typical schematic showing layout considerations applicatio s i for atio wu uu
20 ltc3830/ltc3830-1 sn3830 3830fs applicatio s i for atio wu uu + g1 i max i fb g2 pgnd gnd sense + fb v cc ss freqset shdn comp pv cc2 mbr0530t1 5v 6.8k 1k 100 0.1 f 0.1 f l o 2.5 h q2 c in : sanyo 6tpb330m c out : sanyo 4tpb470m l o : sumida cdep105-2r5 q1, q2: vishay si7892dp c out 470 f 3 3.3v 10a 3830 f012 q1 ltc3830 1 f shutdown nc + 4.7 f pv cc1 sense + c in 330 f 2 + 0.1 f c1 33pf 0.01 f c c 0.01 f r c 18k figure 12. 5v to 3.3v, 10a application
21 ltc3830/ltc3830-1 sn3830 3830fs gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale u package descriptio
22 ltc3830/ltc3830-1 sn3830 3830fs s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 n 2 3 4 n/2 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) u package descriptio
23 ltc3830/ltc3830-1 sn3830 3830fs s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 ?.157 (3.810 ?3.988) note 3 16 15 14 13 .386 ?.394 (9.804 ?10.008) note 3 .228 ?.244 (5.791 ?6.197) 12 11 10 9 s16 0502 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc .245 min n 123 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc3830/ltc3830-1 sn3830 3830fs ? linear technology corporation 2001 lt/tp 0103 2k ? printed in usa related parts part number description comments ltc1430/ltc1430a high power step-down switching regulator controllers ltc3830 is pin-for-pin compatible and is recommended for new designs ltc1530 high power synchronous switching regulator controller so-8 with current limit. no r sense tm required ltc1628 dual high efficiency 2-phase synchronous step-down controller constant frequency, standby 5v and 3.3v ldos, 3.5v v in 36v ltc1702 dual high efficiency 2-phase synchronous step-down controller 550khz, 25mhz gbw voltage mode, v in 7v, no r sense ltc1705 dual 550khz synchronous 2-phase switching regulator provides cpu core, i/o and clk supplies for portable systems controller with 5-bit vid plus ldo ltc1709 2-phase, 5-bit desktop vid synchronous step-down controller current mode, v in to 36v, i out up to 42a ltc1736 synchronous step-down controller with 5-bit mobile vid control fault protection, power good, 3.5v to 36v input, current m ode ltc1773 synchronous step-down controller in ms10 up to 95% efficiency, 550khz, 2.65v v in 8.5v, 0.8v v out v in , synchronizable to 750khz ltc1778 wide operating range/step-down controller, no r sense v in up to 36v, current mode, power good ltc1873 dual synchronous switching regulator with 5-bit desktop vid 1.3v to 3.5v programmable core output plus i/o output ltc1876 2-phase, dual step-down synchronous controller with step-down dc/dc conversion from 3v in , minimum c in and integrated step-up dc/dc regulator c out , uses logic-level n-channel mosfets ltc1929 2-phase, synchronous high efficiency converter current mode ensures accurate current sensing v in up to 36v, with mobile vid i out up to 40a ltc3713 low input voltage, high power, no r sense , step-down minimum v in : 1.5v, uses standard logic-level n-channel synchronous controller mosfets ltc3831 high power synchronous switching regulator controller for v out tracks 1/2 of v in or external reference ddr memory termination ltc3832 synchronous step-down controller 0.6v v out 5v, pin-for-pin compatible with the ltc3830 no r sense is a trademark of linear technology corporation. typical applicatio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical 3.3v to 2.5v, 14a application g1 i max i fb g2 pgnd gnd sense + fb v cc ss freqset shdn comp pv cc2 12v 6.8k 1k 0.1 f l o 1.3 h q2 nc c in : sanyo poscap 6tpb330m c out : sanyo poscap 4tpb470m d1: mbrs330t3 l o : sumida cdep105-1r3 q1, q2: vishay si7892dp d1 c out 470 f 3 2.5v 14a 3.3v 16.5k 1% 16.9k 1% 3830 ta01 q1 ltc3830 10 f shdn 4.7 f pv cc1 sense nc + c in 330 f 2 + 0.1 f c1 33pf 0.01 f 100 c c 1500pf 130k r c 18k

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